The miss penalty to main memory in clock cycle is
( 100 ns ) × ( 4 GHz or 4×109 clock cycles/second )
= ( 100×10-9 second ) × ( 4×109 clock cycles/second )
= 400 clock cycles
The effective CPI with one level of caching is given by
Total CPI = Base CPI + Memory-stall cycles per instruction
For the processor with one level of caching,
Total CPI = 1.0 + 2% × 400 = 9
With two levels of caching, a miss in the primary (or first-level) cache can be satisfied either by the secondary cache or by main memory.
The miss penalty for an access to the second-level cache is
( 5 ns ) × ( 4×109 clock cycles/second ) = 20 clock cycles
Thus, for a two-level cache, total CPI is the sum of the stall cycles from both levels of cache and the base CPI:
Total CPI = 1 + Primary stalls per instruction +
Secondary stalls per instruction
= 1 + 2% × 20 + 0.5% × 400 = 1 + 0.4 + 2.0 = 3.4
Thus, the processor with the secondary cache is faster by
9.0/3.4=2.6.