Data hazards occur when a planned instruction can not execute in the proper clock cycle because data that is needed to execute the instruction is not yet available. One of the data hazards is RAW (Read After Write) hazard. For example, given two instructions
I and J, where I comes before J such as
I: add $1, $2, $3 # $1 is written J: sub $4, $1, $3 # $1 is readInstruction
J should read an operand after it is written by I.
It is called a data dependence.
There are four kinds of data dependence: RAW (Read After Write), WAR (Write After Read), RAR (Read After Read), and WAW (Write After Write).
Hazard occurs when J reads the operand before I writes it, but not all data dependences cause data hazards.
Consider the following sequence with many dependences, shown in red color:
sub $2, $1, $3 # Register $2 written by sub and $4, $2, $5 # 1st operand ($2) depends on sub or $6, $3, $2 # 2nd operand ($2) depends on sub add $7, $2, $2 # 1st ($2) & 2nd ($2) depend on sub sw $8, 10($2) # Base ($2) depends on sub
The figure shows the pipelined dependences in the above sequence.
The first instruction writes into $2, and all the following instructions read $2.
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This register is written in clock cycle 5, so the proper value is unavailable before it. The colored lines from the top datapath to the lower ones show the dependences. Those that must go backward in time are data hazards.
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