They refer to the possibility of erroneous computation when a CPU tries to simultaneously execute multiple instructions which exhibit data dependence.

Data Hazards

Data hazards occur when data is modified. For example, consider the following instructions: sub $1, $2, $3 # $1=$2–$3 andi $2, $1, 3 # $2=$1∧3

In this case in a naive pipeline, $1 will be used in the Execute step (red) by the andi before the sub operation performs WriteBack on it (green).

Control Hazards

Control hazards occur when the processor is told to branch. In such a case, the processor cannot tell in advance whether it should process the next instruction (when it may instead have to move to a distant instruction). This can result in the processor doing unwanted actions. The simplest method of dealing with branches is to stall the pipeline as soon as the branch is detected as follows:

Branch	IF	ID	EX	MEM	WB
Branch successor		IF (stall)	stall	IF	ID	EX	MEM	WB
Branch successor+1					IF	ID	EX	MEM	WB