Graphically Representing Pipelines

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Pipelining can be difficult to understand, since many instructions are simultaneously executing in a single datapath in every clock cycle. To aid understanding, the following figure shows a multiple-clock-cycle pipeline diagram of five instructions. This style of pipeline representation shows the complete execution of instructions in a single figure.

Instructions are listed in instruction execution order from top to bottom, and clock cycles move from left to right.

This representation breaks the register file into two logical parts:

• registers read during register fetch (ID) and
• registers written during write back (WB).

This dual use is represented by drawing the unshaded left half of the register file using dashed lines in the ID stage, when it is not being written, and the unshaded right half in dashed lines in the WB stage, when it is not being read. We assume the register file is written in the first half of the clock cycle and the register file is read during the second half.

Another way of showing the pipelines is given in the figure. It is the traditional multiple-clock-cycle pipeline diagram.