Slide 12.15: Main control signal values

Main Control Signal Values

The table shows the main control signal values, which are completely determined by the opcode fields of the instruction, for various instructions.

Op	`RegDst`	`RegWrite`	`ExtOp`	`ALUSrc`	`Beq`	`Bne`	`J`	`MemRead`	`MemWrite`	`MemtoReg`
R-type
`addi`	0 (`rt`)	1	1 (sign)	1 (Imm)	0	0	0	0	0	0
`slti`	0 (`rt`)	1	1 (sign)	1 (Imm)	0	0	0	0	0	0
`andi`	0 (`rt`)	1	0 (zero)	1 (Imm)	0	0	0	0	0	0
`ori`	0 (`rt`)	1	0 (zero)	1 (Imm)	0	0	0	0	0	0
`xori`	0 (`rt`)	1	0 (zero)	1 (Imm)	0	0	0	0	0	0
`lw`
`sw`	x	0	1 (sign)	1 (Imm)	0	0	0	0	1	x
`beq`
`bne`	x	0	x	0 (`BusB`)	0	1	0	0	0	x
`j`	x	0	x	x	0	0	1	0	0	x

The R-format instructions include add, sub, AND, OR, and slt.
- The source registers are rs and rt, and the destination register is rd; this defines how the signals ALUSrc and RegDst are set.
- An R-type instruction writes a register (RegWrite=1).

For lw and sw,
- The ALUSrc field is set to perform the address calculation.
- The MemRead and MemWrite are set to perform the memory access.
- RegDst and RegWrite are set for a load to cause the result to be stored into the rt register.

The branch instruction is similar to an R-format operation, since it sends the rs and rt registers to the ALU.

Notice that the MemtoReg and RegDst fields are irrelevant when the RegWrite signal is 0. Thus, the entry MemtoReg in the last four rows of the table is replaced with X for “don’t care.”

You are going to jump down from that ledge?
Are you out of your gourd (crazy)?