Clocking Methodology

Clocks are needed in a sequential logic to decide when a state element (register) should be updated. To ensure correctness, a clocking methodology defines when data can be written and read. An edge-triggered clocking methodology is a clocking scheme in which all state changes occur on a clock edge. Combinational logic, state elements, and the clock are closely related. The figure shows the two state elements surrounding a block of combinational logic, which operates in a single clock cycle like 

   add  $t0, $t0, 1
   # $t0 := $t0 + 1
All signals must propagate from state element 1, through the combinational logic, and to state element 2 in the time of one clock cycle.

Any inputs to a state element must reach a stable value (that is, have reached a value from which they will not change until after the clock edge) before the active clock edge causes the state to be updated. An edge-triggered methodology allows a state element to be read and written in the same clock cycle without creating a race that could lead to indeterminate data values.

The clock cycle must be long enough so that the input values are stable when the active clock edge occurs.

Question: Because the register file is both read and written on the same clock cycle, any MIPS data path using edge-triggered writes must have more than one copy of the register file.

Answer:   True   False